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T2901
Bluetooth Single-Chip Transceiver IC
Description
The T2901 is a bipolar intergrated circuit manufactured using TEMIC Semiconductors' advanced UHF process. This IC includes a transceiver for the 2.45 GHz ISM band especially for Bluetooth applications.
Features
D Complete Bluetooth transceiver with fully integrated synthesizer and VCO D TX with advanced closed-loop modulation D TX PA with +3 dBm output power at 2.5 GHz and ramp-signal generator for optional front end D Image rejection mixer D Auxiliary voltage regulator on chip D Supply-voltage range 2.7 V to 3.3 V (6 V with additional external PNP transistor ) D Few low-cost external components / No mechanical tuning required D HP-VQFP-N48 package
Block Diagram
MX IF OUT IN LNA RF IN DEMOD BB FILTER DAC RAMP OUT RAMP SET TX OUT TX PA 3W (PA Ctrl.) f :n RX_ON TX_ON PU_RX/TX PU_PLL RAMP GEN TX / RX SWITCH RSSI VCO GF TX DATA CLOCK DATA ENABLE RSSI IR MIXER IF AMP 1 IF TANK IF AMP 2 BB OUT DEMOD BG_ TANK OUT BLOCK BB CF
PC
PD
MCC
3-WIRE BUS
CP PU VCO VCO REG AUX REG f
RC :n
CTRL LOGIC
VREG GND VS PU VREG REG VS VTUNE VCO VCO REG CTRL UNREG
I_CP SW
CP
LD
REF CLK
Figure 1. Block diagram
Ordering Information
Extended Type Number T2901- PLT T2901- PLQ Package HP-VQFP-N48 HP-VQFP-N48 Remarks Tray Taped and reeled
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Functional Blocks
Name AUX REG BBF CP DAC GF IF AMP1 IF AMP2 IR MIXER LNA Description Auxiliary voltage regulator Baseband filter Charge pump D/A converter for demodulator tuning Gaussian filter for transmit data 1st intermediate frequency amplifier 2nd intermediate frequency amplifier Image rejection mixer Low noise amplifier Name MCC PC PD RAMP GEN RC RSSI TX PA VCO VCO REG Description Modulation-compensation circuit Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Transmit power amplifier Voltage-controlled oscillator Voltage regulator for VCO
Pin Description
GND_PLL VS_MIXER MIXER_OUT2 MIXER_OUT1 RAMP_SET 36 35 34 33 32 TX_DATA PU_PLL PU_RX/TX PU_VCO I_CP_SW TX_ON RX_ON
48 47 46 45 44 43 42 41 40 39 38 37 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_UNREG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DEMOD_TANK2 DEMOD_OUT CP VS_VCO VREG_VCO BG_BLOCK BB_CF GND_VCO VTUNE GND1 DEMOD_TANK1 BB_OUT RAMP OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI
T2901
31 30 29 28 27 26 25
Figure 2. Pinning
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Pin Description (continued)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_UNREG GND_CP VS_CP CP VS_VCO VREG_VCO GND_VCO VTUNE GND1 DEMOD_TANK1 DEMOD_TANK2 DEMOD_OUT BG_BLOCK BB_CF BB_OUT RSSI IF_TANK1 IF_TANK2 GND2 RF_IN1 RF_IN2 GND3 TX_OUT VS_IF IF_IN1 IF_IN2 RAMP OUT RAMP_SET RX_ON TX_ON MIXER_OUT1 MIXER_OUT2 VS_MIXER GND_PLL PU_VCO PU_RX/TX PU_PLL TX_DATA I_CP_SW Function 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input Reference frequency input Lock-detect output Auxiliary voltage regulator power-up input PLL supply voltage Aux. voltage regulator output Aux. voltage regulator control output Aux. voltage regulator supply voltage Charge pump ground Charge pump supply voltage Charge pump output VCO voltage regulator supply voltage VCO voltage regulator control output VCO ground VCO tuning voltage input Ground Demodulator tank circuit Demodulator tank circuit Demodulator output & BB_IN Bandgap blocking Baseband filter corner frequency control input Baseband filter output Received signal strength indicator output IF tank circuit IF tank circuit Ground RF decoupling RF input 2 to the image reject mixer Ground TX PA output IF amplifier supply voltage Differential IF input of the IF amplifier Differential IF input of the IF amplifier Ramp generator output for ext. PA power ramping Slew rate setting of ramping signal RX section power up control input TX section power up control input Differential mixer output of the SAW Differential mixer output of the SAW Mixer supply voltage PLL ground VCO power-up input RX/TX power-up input PLL power-up input TX data input to Gaussian filter and modulation-compensation circuit Charge pump current switch
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Functional Description
Receiver
The RF-input signal at RF_IN is fed to an image-rejection mixer IR MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110 MHz/ 111 MHz. The IF amplifiers IF_AMP1 and IF amplifier IF_AMP2 with an external IF_TANK and an integrated RSSI function fed the signal to the demodulator DEMOD working at f = fIF/2 (55 MHz/ 55.5 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production, an integrated 5-bit Digital-to-Analog (D/A) converter is used to control the on-chip varicap diode. GEN, providing ramp signals at RAMP_OUT for an external power amplifier, is also integrated. The slope of the ramp signal is controlled by a capacitor at RAMP_SET.
Synthesizer
The IR MIXER, the TX DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit Digital-to-Analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX DRIVER, 0/ 90 degreee phase shifter for the IR MIXER and to be used by the PC for the phase detector PD (fPD = 1 MHz). Unlimited multi-slot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC.
Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian filter GF and fet to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX DRIVER. This bus-controlled driver amplifier supplies +3 dBm output power at TX_OUT. A ramp-signal generator RAMP
Power Supply
For minimum interference and maximum signal isolation, an integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current-saving modes are provided.
Absolute Maximum Ratings
All voltages are referred to GND (Pins 11, 16, 18, 28, 31 and 43). Parameter Supply voltage Pins 7, 10, 12, 14, 33 and 42 Logic input voltage Pins 1, 2, 3, 6, 38, 39, 44, 45, 46, 48 Junction temperature Storage temperature Symbol VS_xxx VIN Tjmax Tstg Min. - 0.3 -40 Typ. Max. 6 6 125 125 Unit V V _C _C
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 130 Unit K/W
Operating Range
All voltages are referred to GND (Pins 11, 16, 18, 28, 31 and 43). Parameter Regulated supply voltage Pins 7,12,14, 33 and 42 Unregulated supply voltage Pin 10 Ambient temperature Symbol VS_xxx VS_unreg Tamb Min. 2.7 3.0 -20 Typ. 3.0 +25 Max. 3.3 5.5 +85 Unit V V _C
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Electrical Characteristics
Test conditions (unless otherwise specified) : VS = 3.0 V, Tamb = 25_C. Parameters Power supply Total supply current Standby current LNA + IR mixer Image rejection ratio DSB noise figure Conversion gain Output interception point Receiver sensitivity Input impedance TX PA Max output power Min output power RF leakage IF amplifier Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth of external tank circuit Noise figure RSSI RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output voltage Maximum output voltage Test Conditions / Pins Symbol Pins 7, 10, 12, 14, 33 and 42 TX IS RX IS PU = GND IS Pins 29, 30, 40 and 41 Pins 40 and 41 IRR Pins 40 and 41 NFDSB= NFSSB Rload = 400 (differential) Gconv Pins 40 and 41 OIP3 Pin @ Pin 30, BB out, Pin Pin 24, 12 dB SINAD at 2.45 GHz, Pins 29, 30 Zin Pin 32 Pwr setting = max Pmax Pwr setting = min Pmin In RX mode Pleak Pins 26, 27, 34 and 35 Pins 34 and 35 Zin fl3dB fu3dB Gp Pins 26 and27 BW3dB NF Pins 25, 34 and 35 at IF_IN1 , IF_IN2 Pins 34 and 35 at IF_IN1 , IF_IN2 Pins 34 and 35 at IF_IN1, IF_IN2 Pin 34/35 Slope of the RSSI has to be steady Pin < 30 to 100 dBV, Pin 25 Pin <100 to <30 dBV, Pin 25 Pin <20 dBV at IF_IN1, IF_IN2, Pin 25 Pin =100 dBV at IF_IN1, IF_IN2, Pin 25 Pmin Pmax DR Acc tr tf Vout Vout Min. Typ. 64 69 1 20 30 12 17 -3 -80 5 - j52 0 -47 188 40 313 85 10 12 20 100 80 3 1 1 0.45 2.25 3 -27 5 Max. Unit mA mA A dB dB dB dBm dBm dBm dBm dBm MHz MHz dB MHz dB dBV dBV dB dB s s V V
100
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Electrical Characteristics (continued)
Test conditions (unless otherwise specified) : VS = 3.0 V, Tamb = 25_C. Parameters FM demodulator Co-channel rejection ratio Sensitivity Test Conditions / Pins Pins 19, 20 and 21 Pin = -75 dBm at IR-mixer input Quality factor of external tank circuit approx. 20, fres = fIF/2 Pin 21 Nominal deviation of signal 160 kHz, Pin 21 Pin 21 Pin 21 Pin 21 Pins 23 and 24 Cext = 56 pF Pin 24 Pin 24 Pin 22 Symbol CCRR S Min. Typ. 10 0.6 Max. Unit dB V/MHz
Amplitude of recovered signal Output voltage DC range Output impedance AM rejection ratio Baseband filter 3 dB bandwidth Output voltage range Common-mode input voltage Ramp generator Rise time Fall time Minimum output voltage Maximum output voltage Logic input levels High input level Low input level High input current Low input current Power / standby Power up PU = `1' High input level Standby PU = `0' Low input level Power up PU = `1' High input current
A FMoutDC Zout AMRR PGBW Vout Vin 0.4
200 Vs-0.4 13 t.b.d 1.5 1 1 Vs-1 Vs-1
mVpp V k dB MHz V V
Pin 36 Cramp = 270 pF at Pin 37 tr Cramp = 270 pF at Pin 37 tf Accord. PA ramp input Vmin Accord. PA ramp input Vmax Pins 1, 2, 3, 38, 39, 47 and 48 =`1' ViH =`0' ViL =`1' IiH =`0' IiL Pins 6, 44, 45 and 46 VPU VPU,OFF VPU = 3 V VPU = 5.5 V Pin 6 Pin 46 Pin 46 Pin 44 Pin 45 IPU_REG IPU_PL IPU_PL IPU_VCO IPU_RX/TX IPU,OFF tsoa tssa tsas
5 5 t.b.d. t.b.d. 1.5 -5 -5 2.0 0.7 20 100 200 60 60 30 125 300 80 80 40 150 400 100 100 0.1 1 0.5 5 5
s s V V V V A A V V A A A A A A A s s s
Standby PU = `0' Low input current Settling time VS = 0 active operation Settling time standby active operation Settling time active operation standby
VPU = 0 V VPU = 0.5 V Switched VS = 0 to VS = 3 V Switched PU = 0 to PU = 1 Switched VS = 3 V to VS = 0
< 10 < 10 <2
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Electrical Characteristics (continued)
Test conditions (unless otherwise specified) : VS = 3.0 V, Tamb = 25_C. Parameters Test Conditions / Pins Symbol PLL Scaling factor prescaler SPSC Scaling factor main counter SMC Scaling factor swallow SSC counter External reference input AC-coupled sinewave fREF_CLK frequency @ 20 ppm accuracy, Pin 4 External reference input AC-coupled sinewave, VREF_CLK voltage Pin 4 Total scaling factor Pin 4 SRC reference counter Charge pump active when RX, TX Pin 13 Output current VI_CP_SW = "0" ICP_1 VCP VVS_CP / 2 VI_CP_SW = "1" ICP_5 VCP VVS_CP / 2 Current scaling factor ICP = CPCS x ICP_TYP CPCS (see bus protocol D0 ... D1) Leakage current IL Modulation-compensation circuit @ maximum DSV 78 Oversampling fREF_CLK= 13 MHz OVS Integration counter MAC Current scaling factor (see bus protocol E3 ... E5) MCCS 3-wire bus Clock Pin 1 fclock Gaussian transmit filter, Gaussian shape BT = 0.5 Tx data filter clock fREF_CLK = 13 MHz, TX, fTXFCLK 7 taps in filter GF adjustment range (see bus protocol D6 ... D8) GFCS (for FM deviation adjustm.) Internal VCO Tuning range RX band @ fIF = 111 MHz fVCO,RX Tuning range TX band fVCO,TX Phase noise @ 500 kHz offset Pin 21 NVCO Phase noise, wideband > 2 MHz offset Pin 21 NVCO Tuning input sensitivity Pin 17 SVCO,mod Min. Typ. 32/33 64 0 13 50 13 250 79 31 MHz mVRMS Max. Unit
1 5 80 100 1 -63 60 +63 130 6 6.5 60 130 110
mA mA % pA
% MHz MHz %
2289 2400 -95 -120 50
2389 2500
MHz MHz dBc/Hz dBc/Hz MHz/V
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Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol Min. Internal VCO PRETUNE 4-bit programming (see bus protocol D2 ... D5) Stepwidth fpretune Lock-detect output Pin 5 Lock-detect output, locked = `1' LD test-mode output unlocked = `0' (test modes see bus protocol E0 ... E2) Leakage current VOH = 3.3 V Pin 5 IL Saturation voltage IOL = 0.5 mA Pin 5 VSL Typ. 30 Max. Unit MHz
5 0.4
A V
Table of Switch Settings in Different Modes
Mode PU_PLL, PU_REG PU_RX/TX RX_ON TX_ON PU_VCO VCO, PLL, prescaler, RX/TX switch PA, Ramp Gen, MCC, Gaussian filter LNA, IR mixer, IF amplifier Demodulator, BB-filter Standby 0 0 0 0 0 Off Off Off Off Synthesizer 1 0 0 X 1 On Off Off Off RX Mode 1 1 1 0 1 On Off On On TX Mode 1 1 0 1 1 On On Off Off RSSI 1 1 1 1 1 On Off On Off
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PLL Principle
RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fPD CP VCO Divider by 2 RX: 2289-2389 MHz Divider by 2 TX: 2400-2500 MHz
Phase frequency detector PD
DAC fPD = 1,00 MHz Modulation MCC compensation GF_DATA Gaussian filter GF
Controlled phase shifting
Reference counter RC REF_CLK 13,00 MHz SRC 13
13,00 MHz
1,000 Mbit/s
PLL reference Frequency REF_CLK Baseband controller
TX_DATA
Figure 3. PLL principle Table 1. The following table shows the maximum programmable LO frequencies for RX and TX.
fIF [MHz] min max 111.0 111.0
fRX [MHz] 2159.0 2670.0
fTX [MHz] 2048.0 2559.0
SMC 64 79
SSC 0 31
Preset of MCC and Gaussian Transmit Filter for TX
After programming the PLL (3-wire bus Enable input going to high level) until start of the Data preamble, it is necessary to send a symmetrical alternating 1/0-datastream.
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). In addition to this information, further control bits such as the scaling of charge pump currents as well as internal currents for the Gaussian lowpass filter and modulation-compensation circuit can be transferred.
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After setting the Enable signal to low condition, the data status is transferred bit by bit on the rising edge of the clock signal into the shift register, starting with the MSBbit. When the Enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address-bit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during Enable low condition. The bus then returns to a low-current standby mode until the Enable signal changes to low again.
Bus Protocol Formats
MSB Data bits D22 1 D21 1 D20 0 D19 0 D18 1 D17 0 D16 SC 0 1 1 D15 D14 D13 PS 1 1 D12 D11 0 D10 GF 1 D9 MCC 1 0 D8 D7 GFCS 1 1 1 D6 D5 D4 0 D3 0 D2 0 D1 1 D0 0 LSB Address bit A0 1 1 VCO-DAC CPCS
MC
PA
Standard bit setting:
Word 1 Data bits E10 E9 E8 E7 E6 E5 E4 MCCS 0 1 0 0 0 E3 E2 E1 TEST 0 0 E0 Address bit A0 0 0
DEMODDAC Word 2 1 0 0 0
PLL Settings
MC (Main D22 0 0 0 0 0 ... 0 1 0 1 Counter) D21 D20 0 0 0 0 ... ... 1 1 1 1 D19 0 1 ... 0 1 SMS 64 65 ... 78 79
Gauss Filter and Modulation Compensation Settings
D10 0 1 D9 0 1 D13 SSC *) 0 1 2 ... **) 30 31 0 1 GF (Gaussian Filter) OFF ON MCC (Modulation Compensation Circuit) OFF ON PS (Phase Select ModulationCompensation Circuit) inverted normal
1 1 1 1 1
0 0 0 0 0
D18 0 0 0 ... 1 1
* **
SC (Swallow Counter) D17 D16 D15 D14 0 0 0 0 0 0 0 1 0 0 1 0 ... ... ... ... 1 0 1 1 1 1 1 0
SSC = [D14] x 20 + [D15] x 21 + ... [D218] x 24 SPGD = 32 x SMC + SSC
GFCS (Gaussian Filtered Current Settings) D8 D7 D6 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
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MCCS (Modulation Compensation Current Settings) E5 E4 E3 MCCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
DEMOD DAC Voltage Settings (DEMODDAC)
Demod DAC Voltage (Internal Connection) E10 E9 E8 E7 E6 fIFcenter % 0 0 0 0 0 -3.5 0 0 0 0 1 ... 0 0 0 1 0 ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 3.5
Power Amplifier and Charge Pump Settings
D12 0 0 1 1 PA (Output Power Settings) D11 PA 0 -17 dBm 1 -7 dBm 0 -1 dBm 1 +3 dBm
Test Mode Settings
Test Output Pin (Lock Detect) E1 E0 Signal at lock detect and PLL mode 0 0 Lock detect mode 0 1 PC out divided by two and CP active (phase changed) 1 0 RC out divided by two and CP active (phase changed) 1 1 MCCTEST (REF_CLK divided by 1664) 0 0 CP tristate only 0 1 PC out divided by two and CP high impedance 1 0 RC out divided by two and CP high impedance 1 1 GFTEST (REF_CLK divided by 4)
CPCS (Charge-Pump Current Settings) D1 D0 CPCS 1 0 80% 1 1 90% 0 0 100% 0 1 110%
E2 0 0 0 0
Pretune DAC Voltage Settings
VTUNE = VCC/2 Pretune DAC Voltage (Internal D5 D4 D3 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Rev. A2, 07-Jun-00 Connection) D2 fVCO/% 0 -3.5 1 ... 0 ... 1 ... 0 ... 1 ... 0 ... 1 ... 0 0.0 1 ... 0 ... 1 ... 0 ... 1 ... 0 ... 1 +3.5
1 1 1 1
3-Wire Bus Protocol Pulse Diagram
MSB ENABLE DATA CLOCK LSB
Figure 4.
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3-Wire Bus Protocol Timing Diagram
DATA CLOCK ENABLE TPER TL TS TC TH TT
16525
TEC
Figure 5.
Table 2. Bus signal times
Description Clock period Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to clock Time between two protocols
Symbol TPER TS TH TC TL TEC TT
Min. Value 1/ (6.5 MHz) 60 60 1/ (13 MHz) 3/ (13 MHz) 0 3/ (13 MHz)
Unit s ns ns s s ns s
Bluetooth RX/TX Timing Diagram
Slot-No: 2 n RECEIVE- SLOT Guard- Time Slot-No: 2 n+1 TRANSMIT- SLOT Guard- Time RECEIVE- SLOT
RX-ON TX-ON RAMP
RX-Precharge Time TX-Precharge Time TX-Ramp Time
PLL-Prog 36 Bit/ 6 MHz + 231 ns = 6.231 s TX-Switch Impact 366 625 991
VCO-Freq ~ ~ 366 t=0 366
max. 220 s 259
Freq. Change Period 259 1250 Time/ s
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Typical Application Circuit
Figure 6. Application circuit
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RF Board Measurements
Figure 7. RX mode, Eye pattern with Telefilter TFS111 f = 2450 MHz (signal generator), Pin = -60 dBm, VBB = 1.5 V 130 mV (with optimal tuning of VCODAC and DEMODDAC)
Figure 8. RX / TX mode, Eye pattern Telefilter TFS111 fin = 2450 MHz
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Figure 9. TX spectrum Pout = 1.4 dBm (corrected for cable attenuation: 2 dB) Spurious signal suppression > 60 dBc (typical) PLL loop filter values optimized for settling time < 150 s
Figure 10. TX spectrum Harmonics < 60 dBc
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Package Information
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Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
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We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
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